Typically, an electronic system includes a number of integrated circuit chips that process data and communicate with one another to perform system applications. The integrated circuit chips include devices, such as n-channel metal oxide semiconductor (NMOS) transistors and p-channel metal oxide semiconductor (PMOS) transistors. Often, the integrated circuit chips include NMOS and PMOS transistors in a complementary metal oxide semiconductor (CMOS) configuration. Semiconductor manufacturers continue increasing device densities and speeds to meet the demands of system applications.
Semiconductor manufacturers use stress engineering to enhance device performance. Stresses are introduced into the channel of a device to enhance hole or electron mobility and thereby conductivity through the channel. The stresses affect bandgap and carrier mobility in the silicon and applying the appropriate stress to a channel can significantly improve device performance in terms of the Ion/Ioff ratio. Stress engineering techniques have been used in deep sub-micron process technologies, such as 90 nm processes and 65 nm processes.
PMOS and NMOS devices respond differently to different types of stress. PMOS device performance is enhanced by applying compressive stress to a channel and NMOS device performance is enhanced by applying tensile stress to the channel. Also, stresses can be induced locally, which allows PMOS and NMOS devices to be enhanced independently.
Typically, PMOS and NMOS devices are scaled by increasing the width of the channels. However, stress engineering introduces a width dependence on device performance, such that the maximum on current per width decreases due to stress effects as width is increased.
For these and other reasons there is a need for the present invention.